1. Field of the Invention
The present invention relates to an overcurrent detecting apparatus for detecting the occurrence of an overcurrent by detecting a voltage between terminals of a semiconductor switch which operates to switch on and off, for example, a direct current load circuit for comparison with a reference voltage.
2. Description of the Related Art
In, for example, a load control circuit for controlling power window driving motor installed on a vehicle, a semiconductor switch such as an FET is provided between a direct current power supply and the motor, so as to be switched between on and off to thereby control the driving and stopping of the motor. In addition, in the load control circuit like this, an overcurrent detecting circuit is provided for detecting an overcurrent such as a short circuit current when the overcurrent flows into a load or harness, and when an overcurrent is detected, the semiconductor switched is immediately interrupted so as to protect the whole circuit including the semiconductor switch (for example, refer to JP-A-2002-353794).
FIG. 2 is a circuit diagram which shows the configuration of a conventional load control circuit. As shown in the figure, a load controls circuit includes a direct current power supply VB, a load 101 such as a motor and a switching FET (T101), and a positive terminal of the direct current power supply VB and a drain of the FET (T101) are connected together, a source of the FET (T101) and one end of the load 101 are connected together, and the other end of the load 101 and a negative terminal of the direct current power supply are grounded.
In addition, the drain (voltage V1) of the FET (T101) is grounded via a series connecting circuit of resistors R101, R102. Then, a connecting point (voltage V3) between the resistors R101 and R102 is connected to a negative side input terminal of a comparator CMP101.
Furthermore, the source (voltage V2) of the FET (T101) is connected to a positive side input terminal of the comparator CMP 101. In addition, a driver circuit 102 is provided for controlling the switching of the FET (T101) between on and off, wherein an output terminal of the driver circuit 102 is connected to a gate of the FET (T101) via a resistor 103.
Here, assuming that an on resistance of the FET (T101) is Ron and a drain current is ID, a voltage VDS between the source and the drain of the FET (T101) will be expressed the following equation (1).VDS=V1−V2=Ron*ID  (1)
Then, when an overcurrent flows to the load 101, putting ID in an overcurrent state, the voltage VDS increases, resulting in (V1−V2)>(V1−V3), and an output signal of the comparator CMP 101 is reversed, whereby an overcurrent is detected in a circuit at a subsequent stage (not shown), and a low level voltage is output from the driver circuit 102 to the gate of FET(T101). As a result, since the FET (T101) is switched off, the circuit can be protected from the overcurrent.
Here, assuming that a value of ID which is detected as an overcurrent current is IOVC, and an offset voltage of the comparator CMP101 is Voff, the following equation (2) is obtained.V1−V3=Ron*IOVC+/−Voff  (2),wherein “+/−” means that Voff is add or subtracted from Ron*Lovc.
The following equation (3) is obtained from the equation (2) above.IOVC={(V1−V3)/Ron}+/−(Voff/Ron)  (3)
Here, in case the offset voltage Voff does not exist in the comparator CMP101, namely, Voff=0, the overcurrent detection value IOVC becomes a constant value which is determined by the voltage V3 and the on resistance Ron of the FET (T101). In case the offset voltage Voff exists in the comparator CMP101, however, the overcurrent detection value IOVC varies, and the amount of variation thereof becomes +/−Voff/Ron. Namely, with the offset voltage Voff remaining the same, the smaller the on resistance Ron becomes, the more largely the overcurrent detection value IOVC varies.
The extent or width of variation of the offset voltage (+/−Voff) of the comparator CMP101 depends on the process of fabricating ICs, and with a normal IC, there is provided a variation width of the order of +/−10 [mV].
As has been described above, the offset voltage Voff of the comparator CMP101 constitutes a cause for the variation in the overcurrent detection value and causes a problem that the accuracy of the overcurrent detection value is deteriorated. Furthermore, in the event that there is an increasing tendency that the on resistance Ron of the FET is reduced in the future, the effect of the offset voltage increases further and the reduction in accuracy becomes larger, and to cope with this, there exists an increasing demand for some measures for reducing the effect of the offset voltage of the comparator CMP 101.